The purpose of clock recovery is to lock the bit rate clock to the incoming signal in such a way that the falling edge of the recovered clock is aligned with the edges of the data. This allows the signal to be sampled in the middle of the bit with the rising edge of the recovered clock. This is accomplished by comparing data edges to the falling edge of the recovering clock. If a data edge occurs before the falling edge of the clock, the edge is considered early and the recovered clock is accelerated, as shown in FIG. 1. If the data edge occurs after the falling edge of clock, the edge is considered late and the recovered clock is retarded, as shown in FIG. 2.
When an incoming signal is asymmetric and a sub-harmonic tone of the bit rate clock, and is 180.degree. out of phase with the recovering clock, undesired clock correction can occur, thereby causing undesired clock lock. The data edges will cause a sequence of alternating early-late adjustments in the clock recovery circuit, and the clock will appear to be locked. This is shown in FIG. 3.
It is apparent, therefore, that there is a need for an improved clock recovery circuit.